The present invention relates to a technique for enhancing the speed of executing a program by parallelization in a simulation system.
In recent years, a multi-processor system, which includes a plurality of processors, is used in the fields of scientific and technological calculations, simulation, and the like. In such a system, an application program creates a plurality of processes, assigns the processes to individual processors, and causes the processors to execute the processes in parallel.
A simulation field that has been actively developed these days is simulation software for use in a mechatronics plant of robots, cars, planes, and other vehicles. By virtue of the advancement of electronic components and software technology, main part of robots, cars, planes, and other vehicles is electronically controlled using wires running like a network of neurons and a wireless local area network (LAN).
They are mechanical devices in nature, but also include large amounts of control software installed therein. To develop such products, it is necessary to expend a long time, a huge cost, and many workers in developing and testing control programs.
A known technique for conducting such a test is hardware in the loop simulation (HILS). In particular, the environment for testing electronic control units (ECU) for the overall components of a car is called a full vehicle HILS. For the full vehicle HILS, inside a laboratory, a real ECU is connected to a hardware device dedicated to emulation of an engine, a transmission mechanism, and other components, and a test is conducted under a predetermined scenario. An output of the ECU is input into a monitoring computer, and is presented on a display. A test engineer views information on the display and checks whether an anomalous operation occurs.
Unfortunately, the HILS has to use a dedicated hardware device and physically connect it to the real ECU by wiring, and its preparation is burdensome. A test after replacement with another ECU needs physical reconnection, which takes much time and effort. In addition, because the test uses a real ECU, the test requires a real time. Accordingly, conducting the test with many scenarios takes a considerable time. Typically, the hardware device for emulation in the HILS is highly expensive.
In recent years, techniques utilizing software without the use of the expensive hardware device for emulation have been developed. These techniques are called software in the loop simulation (SILS), and simulates all of the plant, including microcomputers and input and output circuits mounted on the ECU, control scenarios, an engine, and a transmission, using a software simulator. This can carry out a test without hardware of the ECU.
One example of a system that supports construction of such SILS is MATLAB®/Simulink®, which is a simulation modeling system available from The MathWork, Inc. With MATLAB®/Simulink®, a simulation program can be created by arranging functional blocks on a screen using a graphical interface and specifying a process flow with an arrow connecting them. Such a block diagram represents a process corresponding to one time step in simulation, and repeating the process a predetermined number of times can provide a behavior in a time series in a system being a target of the simulation.
In this way, when the block diagram including the functional blocks is created on MATLAB®/Simulink®, it can be converted by, for example, the function of Real-Time Workshop® into source code having the equivalent function in a known computer language, such as the C language. Compiling the source code in C enables simulation to be executed as the SILS in another computer system.
As a computer system including a multi-processor or a multi-core processor becomes commonplace, a technique for dividing a program described in a block diagram into groups called segments, assigning the segments to different processors or cores, and causing them to execute the segments in parallel to increase the speed of execution becomes available.
Japanese Unexamined Patent Application Publication No. 4-211858 discloses a reduction in influences of inter-processor communication on a time for executing processing in execution of divided data flow graphs using a plurality of processors. The reduction is achieved by assigning nodes of the data flow graphs so as to decrease the number of packets flowing among the processors.
Japanese Unexamined Patent Application Publication No. 8-44577 describes a data partitioning method for use in a multi-processor system including a plurality of processors that perform respective assigned tasks and a plurality of memories corresponding to the plurality of processors. The data partitioning method partitions data among the plurality of memories and includes associating each of the tasks with a variable to which the task accesses, identifying the type of the access to the variable by the task, determining an access cost of the access to the variable by the task, and allocating the variable to a memory corresponding to a processor that performs the task at which the access cost is the largest.
Japanese Unexamined Patent Application Publication No. 2011-96107 discloses a parallelization technique. In this technique, in a block diagram, when an output of a functional block having no internal state is used by a functional block A having an internal state, the functional block A is referred to as a use block for the functional block having no internal state. When an output of the functional block A having the internal state is used in calculation as an input of the functional block having no internal state, the functional block A is called a definition block for the functional block having no internal state. By visiting each functional block as a node, the number of sets of use blocks and that of sets of definition blocks are determined for each functional block on the basis of connection relationship between the functional blocks having internal states and the functional blocks having no internal states. Strands are assigned on the basis of the determined numbers. In this way, the block diagram is divided into the strands, thus parallelizing the processing.
From the viewpoint of a numerically solving technique, a model described as a block diagram can be considered to be an explicit representation of ordinary differential equations/state space form (ODE/SSF). An explicit parallel processing technique of solution of ordinary differential equations from this viewpoint is disclosed in Hironori KASAHARA, Toshihisa FUJII, Hiroki HONDA, and Seinosuke NARITA: Parallel Processing of the Solution of Ordinary Differential Equations Using Static Multiprocessor Scheduling Algorithms, Information Processing Society of Japan Transaction, 28(10), pp. 1060-1070 (Oct. 15, 1987). This parallel processing technique of solution of ordinary differential equations includes generating tasks, optimally scheduling the tasks on processors, and generating machine code using the scheduling results and can support various granularities.